Circuit Optimization Techniques

Circuit Optimization Techniques

Before running on real hardware, circuits should be optimized to minimize depth and gate count. This lesson implements key optimization passes used in production transpilers.

Why Circuit Depth Matters

Every gate takes time. On superconducting qubits, single-qubit gate times are ~50 ns and two-qubit gate times are ~300 ns. T1 relaxation times (the time before a qubit forgets its state) are 50–200 μs. A circuit with 500 two-qubit gates takes ~150 μs: right at the edge of decoherence.

The circuit depth is the longest path from input to output, counting gates in series. Qiskit's transpile(circuit, optimization_level=3) applies a battery of optimization passes to reduce depth. Here you will implement the core three.

Optimization Pass 1: Gate Cancellation

If the same involution gate appears twice in a row on the same qubit with nothing between them, both can be removed.

This runs in O(n) time and correctly handles cascades (applying it repeatedly to the output converges).

Optimization Pass 2: RZ Merging

Unlike involutions, RZ gates compose: RZ(θ₁)·RZ(θ₂) = RZ(θ₁+θ₂). Multiple consecutive RZ rotations on the same qubit can be merged into one.

This reduces gate count without changing circuit behavior. If the merged angle is 0 (mod 2π), the gate can be dropped entirely.

Optimization Pass 3: CX Cancellation

CX·CX = I (two identical CX gates on the same qubit pair cancel). Applying this pass reduces two-qubit gate count: the most expensive resource on hardware.