Hardware-Aware Circuit Optimization

Hardware-Aware Circuit Optimization

Given a target quantum state, there are often many circuit implementations. For NISQ hardware, the best implementation minimizes two-qubit gate count and circuit depth.

Why CNOT Count Matters

A circuit with 10 CNOTs has roughly 5-10% error from two-qubit gates alone. Reducing CNOT count from 10 to 4 cuts this error source in half.

GHZ State Optimization

The 3-qubit GHZ state $(|000⟩+|111⟩)/\sqrt{2}$ can be implemented in multiple ways on linear topology (q0-q1-q2):

Naive implementation: H(0), CX(0,1), CX(0,2) Problem: CX(0,2) is not adjacent on linear topology, requiring a SWAP (3 extra CNOTs). Total: 1H + 2CX + 3CX (SWAP) = 1H + 5CX

Standard implementation (cascade along chain): H(0), CX(0,1), CX(1,2) Each CX uses adjacent qubits. No SWAPs needed. Total: 1H + 2CX = 3 gates

Optimal implementation (using middle qubit): H(1), CX(1,0), CX(1,2) The center qubit (q1) is adjacent to both q0 and q2. Both CNOTs share the control qubit q1, so they cannot run in the same time step: the circuit depth is 3. Total: 1H + 2CX = 3 gates at depth 3. The advantage is fewer CNOTs (2 vs 5) and no SWAP routing, not a lower depth.

Circuit Depth vs. Gate Count

Both the cascade and optimal implementations use 3 gates. But:

Fewer CNOTs and no SWAP routing mean less noise. The optimal strategy uses the topology-aware insight that q1 is a hub.