Hardware-Aware Circuit Design Capstone

Hardware-Aware Circuit Design Capstone

In this capstone you do the job of a quantum software engineer preparing a circuit for a real device: build the textbook algorithm, recompile it for the machine's qubit connectivity, measure what noise does to it, and apply error mitigation to claw the signal back. The algorithm is the full 3-qubit quantum Fourier transform, the workhorse behind Shor's algorithm and phase estimation, built from H, controlled-phase, and SWAP gates.

Circuits in this project are written as op lists like ('h', 2) and ('cp', pi/2, 1, 2), replayed onto a circuit by a small harness. That indirection is the point: the same list can be replayed cleanly, replayed with injected noise, or checked gate by gate against a topology constraint, which is exactly how compilers and noise simulators treat circuits internally.

Checkpoint 1: Build the Real QFT

With the counting convention x = q0 + 2q1 + 4q2, the QFT is: H on q2 with controlled phases cp(pi/2) from q1 and cp(pi/4) from q0, then H on q1 with cp(pi/2) from q0, then H on q0, then swap(0, 2) to fix the bit order. The angles halve at each level: those are the binary carries of the Fourier kernel.

Verifying a QFT is subtler than building it. Its outputs are phase patterns with uniform measurement statistics, so Z-basis counts cannot tell a correct QFT from a wrong one. The harness instead gives you a known-good inverse QFT and demands the round trip act as the identity on basis states: prepare $|3⟩$, run your QFT, run the reference inverse, and you must get $|3⟩$ back on every shot. This mirror-circuit trick is how real labs benchmark processors, because it converts an invisible phase error into a visible bit error.

Once the round trip passes, the harness also shows your QFT doing its real job: fed the period-4 state $(|0⟩+|4⟩)/\sqrt{2}$, it produces peaks at exactly 0, 2, 4, 6, the same spectral readout that powers the Shor capstone in Track 4.